1. Field of the Invention
This invention relates to integrated circuit devices and more particularly to the process of manufacture of polysilicon structures with varying values of resistance and the devices produced by the process.
2. Description of Related Art
In the past, to form different values of polysilicon resistance in an integrated circuit for a gate, resistor and capacitor plate, the area and length of the polysilicon need to be modified to meet the criteria, but they increase the cost of manufacturing due to the complex process and the related process issue such as lateral diffusion.
U.S. Pat. No. 5,554,554 of Bastani for "Process for Fabricating Two Loads Having Different Resistance Levels in a Common Layer of Polysilicon" provides a method of forming a first load having a first resistance level and a second load having a second resistance level in a common layer of polysilicon. A layer of polysilicon having a first resistance level is formed. A mask is then formed on the polysilicon layer to define areas of the polysilicon to be implanted with a dopant. The dopant is then implanted into the defined areas of the polysilicon to modify these areas to have a second resistance level. Selected areas of the polysilicon layer are then etched away to form first load regions having the first resistance level and second load regions having the second resistance level.
U.S. Pat. No. 5,705,418 of Liu for "Process for Fabricating Reduced-Thickness High-Resistance Load Resistors in Four-Transistor SRAM Devices" shows a method of forming polysilicon resistors where a silicon dioxide layer is used as an I/I (Ion Implantation) block. An oxidation resistant layer is formed and patterned for exposing regions of the polysilicon layer designated for the formation of the load resistors. A silicon dioxide layer is formed over the surface of the exposed portions of the polysilicon layer, so that the thickness of the designated regions of the polysilicon layer below the silicon dioxide layer is reduced. These designated regions will be formed into the load resistors. The oxidation resistant layer is then removed. Then, impurity ions are implanted into exposed regions of the polysilicon layer, not covered by the silicon dioxide layer, which are designated for forming interconnectors for the memory cell unit.
U.S. Pat. No. 5,514,617 of Liu for "Method of Making a Variable Resistance Polysilicon Conductor for SRAM Devices" shows how to produce resistors using a patterning method with an I/I process with step areas where variable doping results with higher resistance in the steeper areas than the flat areas, plus heavy doping formed in contact areas by doping through openings in a contact mask.
U.S. Pat. No. 4,643,777 of Maeda for "Method of Manufacturing a Semiconductor Device Comprising Resistors of High and Low Resistances" describes a method of forming resistors in portions of a polysilicon layer with portions covered with mask and the other portions covered with a molybdenum film. Then the molybdenum film is subjected to a silicifying step. The result is that those regions of the polysilicon film located under the molybdenum film have a low resistance, while the regions of the polysilicon film covered by the mask have a high resistance value.
See U.S. Pat. No. 5,622,884 of Liu for "Method for Manufacturing a Semiconductor Memory Cell and a Polysilicon Load Resistor of the Semiconductor Memory Cell" formed by depositing a polysilicon layer over an insulating layer. The polysilicon layer is implanted with dopant and is then masked and etched to form a high resistance load resistor.
Also see U.S. Pat. No. 5,474,948 of Yamazaki for "Method of Making a Semiconductor Device Having Polysilicon Resistance Element" which shows polysilicon load resistors.